From 57803ba3f5b10d1214d1089baa401e4b12ef94bf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:23:34 +0100 Subject: sb/amd/sb800: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 35 --------------------------- 1 file changed, 35 deletions(-) (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 89188fddd7..c7ef86a5a1 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -30,10 +30,6 @@ #include -#if CONFIG(SOUTHBRIDGE_AMD_SB800) -#include -#endif - #include "cpu/amd/car/disable_cache_as_ram.c" #if CONFIG(PCI_IO_CFG_EXT) @@ -1041,37 +1037,6 @@ void cpuSetAMDMSR(uint8_t node_id) } } -#if CONFIG(SOUTHBRIDGE_AMD_SB800) - if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { - /* Set up message triggered C1E */ - msr = rdmsr(MSR_INTPEND); - msr.lo &= ~0xffff; /* IOMsgAddr = ACPI_PM_EVT_BLK */ - msr.lo |= ACPI_PM_EVT_BLK & 0xffff; - msr.lo |= (0x1 << 29); /* BmStsClrOnHltEn = 1 */ - if (revision & AMD_DR_GT_D0) { - msr.lo &= ~(0x1 << 28); /* C1eOnCmpHalt = 0 */ - msr.lo &= ~(0x1 << 27); /* SmiOnCmpHalt = 0 */ - } - wrmsr(MSR_INTPEND, msr); - - msr = rdmsr(HWCR_MSR); - msr.lo |= (0x1 << 12); /* HltXSpCycEn = 1 */ - wrmsr(HWCR_MSR, msr); - } - - if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { - if (CONFIG(HAVE_ACPI_TABLES)) - if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && - (nvram)) { - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); - c_state_addr_msr.lo = ACPI_CPU_P_LVL2; - wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); - } - } -#endif - if (revision & AMD_FAM15_ALL) { enable_cpb = 1; if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) -- cgit v1.2.3