From 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 8 Jul 2013 16:23:54 -0600 Subject: cpu: Fix spelling Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/amd/car/post_cache_as_ram.c | 4 ++-- src/cpu/amd/dualcore/amd_sibling.c | 4 ++-- src/cpu/amd/geode_gx2/cpubug.c | 6 +++--- src/cpu/amd/geode_gx2/cpureginit.c | 4 ++-- src/cpu/amd/geode_lx/cpubug.c | 2 +- src/cpu/amd/model_10xxx/defaults.h | 2 +- src/cpu/amd/model_10xxx/fidvid.c | 6 +++--- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 2 +- src/cpu/amd/model_fxx/powernow_acpi.c | 6 +++--- src/cpu/amd/mtrr/amd_mtrr.c | 4 ++-- src/cpu/amd/quadcore/amd_sibling.c | 4 ++-- 13 files changed, 25 insertions(+), 25 deletions(-) (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 68e7c09ad3..18c278e41a 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -88,7 +88,7 @@ static void post_cache_as_ram(void) #endif #if 1 { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ unsigned v_esp; __asm__ volatile ( "movl %%esp, %0\n\t" @@ -123,7 +123,7 @@ static void post_cache_as_ram(void) /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%esp\n\t" ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) - /* discard all registers (eax is used for %0), so gcc redo everything + /* discard all registers (eax is used for %0), so gcc redoes everything after the stack is moved */ : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" ); diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 13b9e378f3..b3df0a36e7 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -91,10 +91,10 @@ unsigned get_apicid_base(unsigned ioapic_num) } #endif - //contruct apicid_base + //Construct apicid_base if((!disable_siblings) && (siblings>0) ) { - /* for 8 way dual core, we will used up apicid 16:16, actualy 16 is not allowed by current kernel + /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */ diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index 54d7e0e8d2..eddc92408e 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -163,7 +163,7 @@ static void eng2900(void) * clocks when CPU is snooped. Because setting XSTATE to 0 * overrides any other XSTATE action, the code will always * stall for 4 GeodeLink clocks after a snoop request goes - * away even if it occured a clock or two later than a + * away even if it occurred a clock or two later than a * different snoop; the stall signal will never 'glitch high' * for only one or two CPU clocks with this code. */ @@ -201,7 +201,7 @@ static void eng2900(void) msr.lo = 0x30000; wrmsr(MSR_GLCP + 0x0073, msr); - /* Writing action number 5: STALL_CPU_PIPE when exitting idle + /* Writing action number 5: STALL_CPU_PIPE when exiting idle state or not in idle state */ msr.hi = 0; msr.lo = 0x00430000; @@ -293,7 +293,7 @@ static void bug118339(void) * * PBZ 3659: * The MC reordered transactions incorrectly and breaks coherency. - * Disable reording and take a potential performance hit. + * Disable reordering and take a potential performance hit. * This is safe to do here and not in MC init since there is nothing * to maintain coherency with and the cache is not enabled yet. */ diff --git a/src/cpu/amd/geode_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c index 0fc852d531..e0ecd62722 100644 --- a/src/cpu/amd/geode_gx2/cpureginit.c +++ b/src/cpu/amd/geode_gx2/cpureginit.c @@ -15,7 +15,7 @@ void cpuRegInit (void) /* Set up GLCP to grab BTM data. */ msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; - msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */ + msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ /* Turn off debug clock */ @@ -119,7 +119,7 @@ void cpuRegInit (void) wrmsr(msrnum, msr); } -/* FPU impercise exceptions bit */ +/* FPU imprecise exceptions bit */ { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index 4110454566..ebadec7f7a 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -67,7 +67,7 @@ static void pcideadlock(void) /***/ /** PBZ 3659:*/ /** The MC reordered transactions incorrectly and breaks coherency.*/ -/** Disable reording and take a potential performance hit.*/ +/** Disable reordering and take a potential performance hit.*/ /** This is safe to do here and not in MC init since there is nothing*/ /** to maintain coherency with and the cache is not enabled yet.*/ /***/ diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index f7b8b2f9e1..3d33dda029 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -54,7 +54,7 @@ static const struct { { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR, 0x00000000, 0x00000000, - 0x00000000, 0x00000C00 }, /* Errata 326 */ + 0x00000000, 0x00000C00 }, /* Erratum 326 */ { NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 0x00000000, 1 << 22, diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index ebe44dd76a..4297c90460 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -68,7 +68,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 9.- TODO Requires information on current delivery capability (depends on mainboard and maybe power supply ?). One might use a config - option with the maximum number of Ampers that the board can deliver to CPU. + option with the maximum number of Amperes that the board can deliver to CPU. 10.- [Multiprocessor] TODO 2.4.2.12 [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, @@ -79,7 +79,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway) 12.- generate ACPI for p-states. FIXME - Needs more assesment. There's some kind of fixed support that + Needs more assessment. There's some kind of fixed support that does not seem to depend on CPU revision or actual MSRC001_00[68:64] as BKDG apparently requires. http://www.coreboot.org/ACPI#CPU_Power_Management @@ -935,7 +935,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) static void finalPstateChange(void) { - /* Enble P0 on all cores for best performance. + /* Enable P0 on all cores for best performance. * Linux can slow them down later if need be. * It is safe since they will be in C1 halt * most of the time anyway. diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 3d5ddcfb35..eb047b8db2 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -424,7 +424,7 @@ static void start_node(u8 node) /** * static void setup_remote_node(u32 node) * - * Copy the BSP Adress Map to each AP. + * Copy the BSP Address Map to each AP. */ static void setup_remote_node(u8 node) { diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 06ff636659..e68611bca8 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -496,7 +496,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) continue; if ((readback & 0xff) == 2) { timeout = 0; - break; /* target ap is stage 2, it's FID has beed set */ + break; /* target ap is stage 2, its FID has been set */ } } @@ -603,7 +603,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* For all APs ( We know the APIC ID of all AP even the APIC ID is lifted) * send signal to the AP it could change it's fid/vid */ - /* remote read singnal from AP that AP is done */ + /* remote read signal from AP that AP is done */ fv.common_fidvid &= 0xffff00; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index a18b982bdb..42c6f95119 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -509,7 +509,7 @@ static void model_fxx_init(device_t dev) id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set - /* Is this a bad location? In particular can another node prefecth + /* Is this a bad location? In particular can another node prefetch * data from this node before we have initialized it? */ if (id.coreid == 0) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 820d4262e6..af1e24b094 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -75,7 +75,7 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid #if CONFIG_K8_REV_F_SUPPORT /* -* Details about this algorithm , refert to BDKG 10.5.1 +* Details about this algorithm , refer to BDKG 10.5.1 * Two parts are included, the another is the DSDT reconstruction process */ @@ -202,7 +202,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) goto write_pstates; } - /* Get the multipier of the fid frequency */ + /* Get the multiplier of the fid frequency */ /* * Fid multiplier is always 100 revF and revG. */ @@ -316,7 +316,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_num++; } - /* Constuct P[Min] State */ + /* Construct P[Min] State */ if (Max_fid == 0x2A && Max_vid != 0x0) { Pstate_fid[Pstate_num] = 0x2; Pstate_feq[Pstate_num] = diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 2f3e6e340f..033ec53d3a 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -128,10 +128,10 @@ void amd_setup_mtrrs(void) } /* Now that I have mapped what is memory and what is not - * Setup the mtrrs so we can cache the memory. + * Set up the mtrrs so we can cache the memory. */ - // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need + // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need // variable MTRR to span memory above 4GB // Lower revisions K8 need variable MTRR over 4GB x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1); diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index e0d173dd79..d653a85d5a 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -95,10 +95,10 @@ u32 get_apicid_base(u32 ioapic_num) nb_cfg_54 = read_nb_cfg_54(); - //contruct apicid_base + //Construct apicid_base if((!disable_siblings) && (siblings>0) ) { - /* for 8 way dual core, we will used up apicid 16:16, actualy + /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. -- cgit v1.2.3