From de56a66e73442d1fb132f466bb556563bee0639d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:51:51 +0100 Subject: cpu/amd/fam10: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/cpu/amd/quadcore/amd_sibling.c | 118 ------------------------------------- 1 file changed, 118 deletions(-) delete mode 100644 src/cpu/amd/quadcore/amd_sibling.c (limited to 'src/cpu/amd/quadcore/amd_sibling.c') diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c deleted file mode 100644 index ac637ff817..0000000000 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct device *get_node_pci(u32 nodeid, u32 fn); - -#if 0 -static int first_time = 1; -#endif - -#include "quadcore_id.c" - -static u32 get_max_siblings(u32 nodes) -{ - struct device *dev; - u32 nodeid; - u32 siblings = 0; - - //get max siblings from all the nodes - for (nodeid = 0; nodeid < nodes; nodeid++) { - int j; - dev = get_node_pci(nodeid, 3); - j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if (siblings < j) - siblings = j; - } - - return siblings; -} - - -static void enable_apic_ext_id(u32 nodes) -{ - struct device *dev; - u32 nodeid; - - //enable APIC_EXIT_ID all the nodes - for (nodeid = 0; nodeid < nodes; nodeid++) { - u32 val; - dev = get_node_pci(nodeid, 0); - val = pci_read_config32(dev, 0x68); - val |= (1 << 17)|(1 << 18); - pci_write_config32(dev, 0x68, val); - } -} - - -u32 get_apicid_base(u32 ioapic_num) -{ - u32 apicid_base; - u32 siblings; - u32 nb_cfg_54; - - u32 disable_siblings = !CONFIG(LOGICAL_CPUS); - - get_option(&disable_siblings, "multi_core"); - - siblings = get_max_siblings(sysconf.nodes); - - if (sysconf.bsp_apicid > 0) { - // IOAPIC could start from 0 - return 0; - } else if (sysconf.enabled_apic_ext_id) { - // enabled ext id but bsp = 0 - return 1; - } - - nb_cfg_54 = read_nb_cfg_54(); - - - //Construct apicid_base - - if ((!disable_siblings) && (siblings > 0)) { - /* for 8 way dual core, we will used up apicid 16:16, actually - 16 is not allowed by current kernel and the kernel will try - to get one that is small than 16 to make IOAPIC work. I don't - know when the kernel can support 256 APIC id. - (APIC_EXT_ID is enabled) */ - - //4:10 for two way 8:12 for four way 16:16 for eight way - //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes - //for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes : - 8 * siblings + sysconf.nodes; - - } else { - apicid_base = sysconf.nodes; - } - - if ((apicid_base+ioapic_num-1) > 0xf) { - // We need to enable APIC EXT ID - printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n"); - enable_apic_ext_id(sysconf.nodes); - } - - return apicid_base; -} -- cgit v1.2.3