From dc35d2a693ade7e2afa8fa55c21eb61e17078017 Mon Sep 17 00:00:00 2001 From: Michał Kopeć Date: Tue, 30 Nov 2021 17:40:52 +0100 Subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Disable LEGACY_SMP_INIT to enable PARALLEL_MP. Also remove a large amount of APIC code that is now unnecessary. TEST=Boot on PC Engines apu3 Boot time reduced from 1.707 seconds to 1.620 seconds average across 5 coldboots. Inspired by CB:59693 Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/59808 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/cpu/amd/pi/00730F01/model_16_init.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'src/cpu/amd/pi/00730F01') diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a5a8064737..f84b03ab3b 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -23,21 +23,6 @@ static void model_16_init(struct device *dev) msr_t msr; u32 siblings; - /* - * All cores are initialized sequentially, so the solution for APs will be created - * before they start. - */ - x86_setup_mtrrs_with_detect(); - /* - * Enable ROM caching on BSP we just lost when creating MTRR solution, for faster - * execution of e.g. AmdInitLate - */ - if (boot_cpu()) { - mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); - } - x86_mtrr_check(); - /* zero the machine check error status registers */ mca_clear_status(); -- cgit v1.2.3