From 7c302cf20859592a32e19fb6eb434dfb06b1d3c3 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 21 Apr 2023 17:57:17 +0200 Subject: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c Now that the code is in a much better shape and uses native coreboot functionality to perform the initialization, rename the file from fixme.c to cpu_io_init.c to be more descriptive of what it does. Signed-off-by: Felix Held Change-Id: I97d1ac2b12c624210c570f189f825409bd64f318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74659 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/amd/pi/00730F01/Makefile.inc | 4 ++-- src/cpu/amd/pi/00730F01/cpu_io_init.c | 33 +++++++++++++++++++++++++++++++++ src/cpu/amd/pi/00730F01/fixme.c | 33 --------------------------------- 3 files changed, 35 insertions(+), 35 deletions(-) create mode 100644 src/cpu/amd/pi/00730F01/cpu_io_init.c delete mode 100644 src/cpu/amd/pi/00730F01/fixme.c (limited to 'src/cpu/amd/pi/00730F01') diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 51f90ef6e9..ae5a20bbf4 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -romstage-y += fixme.c +romstage-y += cpu_io_init.c -ramstage-y += fixme.c ramstage-y += chip_name.c +ramstage-y += cpu_io_init.c ramstage-y += model_16_init.c ramstage-y += update_microcode.c diff --git a/src/cpu/amd/pi/00730F01/cpu_io_init.c b/src/cpu/amd/pi/00730F01/cpu_io_init.c new file mode 100644 index 0000000000..9724133ab7 --- /dev/null +++ b/src/cpu/amd/pi/00730F01/cpu_io_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void amd_initcpuio(void) +{ + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + pci_write_config32(_SOC_DEV(0x18, 1), 0xf4, 1); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. Last address before processor local APIC + * at FEE00000, set NP (non-posted) bit. + */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x84, + ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8 | (1 << 7)); + /* lowest NP address is HPET at FED00000 */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); + + /* Map the remaining PCI hole as posted MMIO. */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, + ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); + + /* Send all IO (0000-FFFF) to southbridge. */ + pci_write_config32(_SOC_DEV(0x18, 1), 0xc4, 0x0000f000); + pci_write_config32(_SOC_DEV(0x18, 1), 0xc0, 0x00000003); +} diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c deleted file mode 100644 index 9724133ab7..0000000000 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -void amd_initcpuio(void) -{ - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - pci_write_config32(_SOC_DEV(0x18, 1), 0xf4, 1); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. Last address before processor local APIC - * at FEE00000, set NP (non-posted) bit. - */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x84, - ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8 | (1 << 7)); - /* lowest NP address is HPET at FED00000 */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); - - /* Map the remaining PCI hole as posted MMIO. */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, - ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); - - /* Send all IO (0000-FFFF) to southbridge. */ - pci_write_config32(_SOC_DEV(0x18, 1), 0xc4, 0x0000f000); - pci_write_config32(_SOC_DEV(0x18, 1), 0xc0, 0x00000003); -} -- cgit v1.2.3