From 5005bb06c17461ef75cd1fef55c24dffaa05e580 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 11 Apr 2011 20:17:22 +0000 Subject: Unify use of post_code Signed-off-by: Alexandru Gagniuc Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_gx2/cache_as_ram.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/cpu/amd/model_gx2') diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/model_gx2/cache_as_ram.inc index 433576c737..0af2fdf488 100644 --- a/src/cpu/amd/model_gx2/cache_as_ram.inc +++ b/src/cpu/amd/model_gx2/cache_as_ram.inc @@ -27,6 +27,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include +#include /*************************************************************************** /** /** DCacheSetup @@ -184,7 +185,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +202,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt -- cgit v1.2.3