From 1d80e5101772220213f64a8845b21fa063710995 Mon Sep 17 00:00:00 2001 From: Xavi Drudis Ferran Date: Sun, 27 Feb 2011 23:50:30 +0000 Subject: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], Northbridge/core synchronization FIFO pointer adjust, to its own function. Signed-off-by: Xavi Drudis Ferran Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_10xxx/fidvid.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'src/cpu/amd/model_10xxx') diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 60df8b55ce..8f102c5831 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -258,6 +258,17 @@ static void config_power_ctrl_misc_reg(device_t dev) { } } + +static void config_nb_syn_ptr_adj(device_t dev) { + /* Note the following settings are additional from the ported + * function setFidVidRegs() + */ + u32 dword = pci_read_config32(dev, 0xDc); + dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ + pci_write_config32(dev, 0xdc, dword); + +} + static void prep_fid_change(void) { u32 dword; @@ -281,13 +292,8 @@ static void prep_fid_change(void) config_clk_power_ctrl_reg0(i); config_power_ctrl_misc_reg(dev); - - /* Note the following settings are additional from the ported - * function setFidVidRegs() - */ - dword = pci_read_config32(dev, 0xDc); - dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ - pci_write_config32(dev, 0xdc, dword); + + config_nb_syn_ptr_adj(dev); /* Rev B settings - FIXME: support other revs. */ dword = 0xA0E641E6; -- cgit v1.2.3