From 1a5f1c89d752bf906f7428f96c5ff624a1baba97 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Wed, 31 Oct 2018 08:06:12 +0100
Subject: cpu/amd: Use common AMD's MSR

This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd)

Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29369
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/amd/microcode/microcode.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/cpu/amd/microcode')

diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 68b6953be8..29a550d529 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/microcode.h>
 #include <cbfs.h>
 #include <arch/io.h>
@@ -121,7 +122,7 @@ static void apply_microcode_patch(const struct microcode *m)
 	msr.hi = 0;
 	msr.lo = (uint32_t)m;
 
-	wrmsr(0xc0010020, msr);
+	wrmsr(MSR_PATCH_LOADER, msr);
 
 	UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
 
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