From 7916f4cef62bf032af86368a9df45db833d09b79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 9 Feb 2012 16:07:41 +0200 Subject: AMD Geode cpus: apply un-written naming rules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Rename directories and Kconfig as follows: model_lx -> geode_lx model_gx1 -> geode_gx1 model_gx2 -> geode_gx2 Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/amd/geode_gx2/Kconfig | 58 ++++++ src/cpu/amd/geode_gx2/Makefile.inc | 9 + src/cpu/amd/geode_gx2/cache_as_ram.inc | 208 ++++++++++++++++++++ src/cpu/amd/geode_gx2/cpubug.c | 349 +++++++++++++++++++++++++++++++++ src/cpu/amd/geode_gx2/cpureginit.c | 129 ++++++++++++ src/cpu/amd/geode_gx2/geode_gx2_init.c | 46 +++++ src/cpu/amd/geode_gx2/syspreinit.c | 20 ++ 7 files changed, 819 insertions(+) create mode 100644 src/cpu/amd/geode_gx2/Kconfig create mode 100644 src/cpu/amd/geode_gx2/Makefile.inc create mode 100644 src/cpu/amd/geode_gx2/cache_as_ram.inc create mode 100644 src/cpu/amd/geode_gx2/cpubug.c create mode 100644 src/cpu/amd/geode_gx2/cpureginit.c create mode 100644 src/cpu/amd/geode_gx2/geode_gx2_init.c create mode 100644 src/cpu/amd/geode_gx2/syspreinit.c (limited to 'src/cpu/amd/geode_gx2') diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig new file mode 100644 index 0000000000..0e25542582 --- /dev/null +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_AMD_GEODE_GX2 + bool + +if CPU_AMD_GEODE_GX2 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select CACHE_AS_RAM + +config DCACHE_RAM_BASE + hex + default 0xc8000 + +config DCACHE_RAM_SIZE + hex + default 0x04000 + +config GEODE_VSA + bool + default y + select PCI_OPTION_ROM_RUN_REALMODE + +config GEODE_VSA_FILE + bool "Add a VSA image" + help + Select this option if you have an AMD Geode GX2 vsa that you would + like to add to your ROM. + + You will be able to specify the location and file name of the + image later. + +config VSA_FILENAME + string "AMD Geode GX2 VSA path and filename" + depends on GEODE_VSA_FILE + default "gpl_vsa_gx_102.bin" + help + The path and filename of the file to use as VSA. + +endif # CPU_AMD_GEODE_GX2 diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc new file mode 100644 index 0000000000..b70537accf --- /dev/null +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -0,0 +1,9 @@ +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += geode_gx2_init.c +ramstage-y += cpubug.c + +cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc new file mode 100644 index 0000000000..0af2fdf488 --- /dev/null +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) + +#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */ +#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ +#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ +#include +#include +/*************************************************************************** +/** +/** DCacheSetup +/** +/** Setup data cache for use as RAM for a stack. +/** +/** Max. size data cache =0x4000 (16KB) +/** +/***************************************************************************/ +DCacheSetup: + /* Save the BIST result */ + movl %eax, %ebx + + invd + /* set cache properties */ + movl $CPU_RCONF_DEFAULT, %ecx + rdmsr + movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ + wrmsr + + /* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */ + movl $CPU_DM_CONFIG0, %ecx + rdmsr + andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ + wrmsr + + /* Get cleaned up. */ + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ + /* remember, there is NO stack yet... */ + + /* Tell cache we want to fill WAY 0 starting at the top */ + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_INDEX, %ecx + wrmsr + + /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ + movl $GX2_STACK_BASE, %ebp /* init to start address */ + orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ + + /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ + movl $GX2_NUM_CACHELINES, %edi +DCacheSetupFillWay: + + /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ + /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ + movw $0x04, %si + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_DATA, %ecx +DCacheSetup_quadWordLoop: + wrmsr + decw %si + jnz DCacheSetup_quadWordLoop + + /* Set the tag for this line,need to do this for every new cache line to validate it! */ + /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ + xorl %edx, %edx + movl %ebp, %eax + movl $CPU_DC_TAG, %ecx + wrmsr + + /* switch to next line */ + /* lines are in Bits8:2 */ + /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */ + wrmsr + + decl %edi + jnz DCacheSetupFillWay + + /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ + addl $GX2_CACHEWAY_SIZE, %ebp + cmpl $GX2_STACK_END, %ebp + jge leave_DCacheSetup + movl $GX2_NUM_CACHELINES, %edi + + /* switch to next way */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x01, %eax + andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */ + wrmsr + + jmp DCacheSetupFillWay + +leave_DCacheSetup: + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ + /* Memory reads and writes will all hit in the cache. */ + /* Cache updates and memory write-backs will not occur ! */ + movl %cr0, %eax + orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ + movl %eax, %cr0 + + /* Now point sp to the cached stack. */ + /* The stack will be fully functional at this location. No system memory is required at all ! */ + /* set up the stack pointer */ + movl $GX2_STACK_END, %eax + movl %eax, %esp + + /* test the stack*/ + movl $0x0F0F05A5A, %edx + pushl %edx + popl %ecx + cmpl %ecx, %edx + je DCacheSetupGood + + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad +DCacheSetupGood: + /* Go do early init and memory setup */ + + /* Restore the BIST result */ + movl %ebx, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function */ + call main +done_cache_as_ram_main: + + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi + + /* Clear the cache out to ram */ + wbinvd + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + + /* TODO For suspend/resume the cache will have to live between + * CONFIG_RAMBASE and CONFIG_RAMTOP + */ + + cld /* clear direction flag */ + + /* copy coreboot from it's initial load location to + * the location it is compiled to run at. + * Normally this is copying from FLASH ROM to RAM. + */ + movl %ebp, %esi + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c new file mode 100644 index 0000000000..473766c8a4 --- /dev/null +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -0,0 +1,349 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if 0 +void bug645(void) +{ + msr_t msr; + rdmsr(CPU_ID_CONFIG); + msr.whatever |= ID_CONFIG_SERIAL_SET; + wrmsr(msr); +} + +void bug573(void) +{ + msr_t msr; + msr = rdmsr(MC_GLD_MSR_PM); + msr.eax &= 0xfff3; + wrmsr(MC_GLD_MSR_PM); +} +#endif + +/* pcideadlock + * + * Bugtool #465 and #609 + * PCI cache deadlock + * There is also fix code in cache and PCI functions. This bug is very is pervasive. + */ +static void pcideadlock(void) +{ + msr_t msr; + + /* forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting + * for PCI writes to complete. + */ + msr = rdmsr(CPU_DM_CONFIG0); + msr.hi &= ~(7<= CPU_REV_2_1){ + msrnum = CPU_PF_BTB_CONF; + msr = rdmsr(msrnum); + msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET; + wrmsr(msrnum, msr); + } + +/* FPU impercise exceptions bit */ + { + msrnum = CPU_FPU_MSR_MODE; + msr = rdmsr(msrnum); + msr.lo |= FPU_IE_SET; + wrmsr(msrnum, msr); + } +} diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c new file mode 100644 index 0000000000..7e481b5390 --- /dev/null +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -0,0 +1,46 @@ +#include +#include +#include +#include +#include +#include +#include + +static void vsm_end_post_smi(void) +{ + __asm__ volatile ( + "push %ax\n" + "mov $0x5000, %ax\n" + ".byte 0x0f, 0x38\n" + "pop %ax\n" + ); +} + +static void geode_gx2_init(device_t dev) +{ + printk(BIOS_DEBUG, "geode_gx2_init\n"); + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Enable the local cpu apics */ + //setup_lapic(); + + vsm_end_post_smi(); + + printk(BIOS_DEBUG, "geode_gx2_init DONE\n"); +}; + +static struct device_operations cpu_dev_ops = { + .init = geode_gx2_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_NSC, 0x0552 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c new file mode 100644 index 0000000000..814034823c --- /dev/null +++ b/src/cpu/amd/geode_gx2/syspreinit.c @@ -0,0 +1,20 @@ +/* StartTimer1 + * + * Entry: none + * Exit: Starts Timer 1 for port 61 use + * Destroys: Al, + */ +static void StartTimer1(void) +{ + outb(0x56, 0x43); + outb(0x12, 0x41); +} + +void SystemPreInit(void) +{ + /* they want a jump ... */ +#if !CONFIG_CACHE_AS_RAM + __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); +#endif + StartTimer1(); +} -- cgit v1.2.3