From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/cpu/amd/family_10h-family_15h/tsc_freq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/cpu/amd/family_10h-family_15h/tsc_freq.c') diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c index 4aea1a02c9..63b4ac0e8a 100644 --- a/src/cpu/amd/family_10h-family_15h/tsc_freq.c +++ b/src/cpu/amd/family_10h-family_15h/tsc_freq.c @@ -15,6 +15,7 @@ #include #include +#include #include unsigned long tsc_freq_mhz(void) @@ -29,7 +30,7 @@ unsigned long tsc_freq_mhz(void) * to MHz. See also the Family 15h BKDG * Rev. 3.14 page 569. */ - msr = rdmsr(0xc0010064); + msr = rdmsr(PSTATE_0_MSR); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; -- cgit v1.2.3