From 0867062412dd4bfe5a556e5f3fd85ba5b682d79b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 30 Jun 2009 15:17:49 +0000 Subject: This patch unifies the use of config options in v2 to all start with CONFIG_ It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/car/cache_as_ram.inc | 30 +++++++++++++++--------------- src/cpu/amd/car/clear_init_ram.c | 6 +++--- src/cpu/amd/car/copy_and_run.c | 4 ++-- src/cpu/amd/car/disable_cache_as_ram.c | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 18 +++++++++--------- 5 files changed, 30 insertions(+), 30 deletions(-) (limited to 'src/cpu/amd/car') diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 94990a66f7..50b78d0c92 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -18,13 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CacheSize DCACHE_RAM_SIZE +#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) /* leave some space for global variable to pass to RAM stage */ -#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE +#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -/* for CAR_FAM10 */ +/* for CONFIG_CAR_FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ #define MSR_FAM10 0xC001102A @@ -72,7 +72,7 @@ cache_as_ram_setup: cvtsd2si %xmm3, %ebx /* hope we can skip the double set for normal part */ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx @@ -248,10 +248,10 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#endif /* USE_FAILOVER_IMAGE == 1*/ +#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) /* disable cache */ movl %cr0, %eax orl $(1 << 30),%eax @@ -259,25 +259,25 @@ clear_fixed_var_mtrr_out: #endif -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x203, %ecx - movl $0xff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for K8 (CPU_ADDR_BITS = 40) */ + movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */ jmp_if_k8(wbcache_post_fam10_setup) - movl $0xffff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for FAM10 (CPU_ADDR_BITS = 48) */ + movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Set the default memory type and enable fixed and variable MTRRs */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx @@ -313,7 +313,7 @@ fam10_end_part1: movb $0xA2, %al outb %al, $0x80 -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Read the range with lodsl*/ cld movl $CacheBase, %esi @@ -325,7 +325,7 @@ fam10_end_part1: xorl %eax, %eax rep stosl -#endif /*USE_FAILOVER_IMAGE == 1*/ +#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/ /* set up the stack pointer */ movl $(CacheBase + CacheSize - GlobalVarSize), %eax diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c index 8b97129ec6..0b50480142 100644 --- a/src/cpu/amd/car/clear_init_ram.c +++ b/src/cpu/amd/car/clear_init_ram.c @@ -7,11 +7,11 @@ static void __attribute__((noinline)) clear_init_ram(void) // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); + clear_memory( CONFIG_RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE)); #endif } diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c index 437b91d4ac..f495f6dbba 100644 --- a/src/cpu/amd/car/copy_and_run.c +++ b/src/cpu/amd/car/copy_and_run.c @@ -8,7 +8,7 @@ void cbfs_and_run_core(char*, unsigned ebp); static void copy_and_run(void) { -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_ram", 0); # else cbfs_and_run_core("normal/coreboot_ram", 0); @@ -19,7 +19,7 @@ static void copy_and_run(void) static void copy_and_run_ap_code_in_car(unsigned ret_addr) { -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_apc", ret_addr); # else cbfs_and_run_core("normal/coreboot_apc", ret_addr); diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f5f831270..a5113474d3 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -16,7 +16,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "wrmsr\n\t" -#if DCACHE_RAM_SIZE > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 "movl $0x268, %ecx\n\t" /* fix4k_c0000*/ "wrmsr\n\t" #endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 89366e0e33..9e988f02be 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -64,7 +64,7 @@ static void post_cache_as_ram(void) set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); /* from here don't store more data in CAR */ @@ -76,14 +76,14 @@ static void post_cache_as_ram(void) ); #endif - memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline + memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp #if 0 __asm__ volatile ( @@ -102,18 +102,18 @@ static void post_cache_as_ram(void) disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) + clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) print_debug("Done\r\n"); // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif set_sysinfo_in_ram(1); // So other core0 could start to train mem -#if MEM_TRAIN_SEQ == 1 -// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); +#if CONFIG_MEM_TRAIN_SEQ == 1 +// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c -- cgit v1.2.3