From 730a043fb6cb4dd3cb5af8f8640365727b598648 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 16 Oct 2015 13:51:51 -0500 Subject: cpu/amd: Add initial AMD Family 15h support TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/amd/car/post_cache_as_ram.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'src/cpu/amd/car/post_cache_as_ram.c') diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 61d47a2ed9..49b9ee3fe3 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -84,18 +84,19 @@ static void prepare_ramstage_region(void *resume_backup_memory) static void vErrata343(void) { #ifdef BU_CFG2_MSR - msr_t msr; - unsigned int uiMask = 0xFFFFFFF7; + msr_t msr; + unsigned int uiMask = 0xFFFFFFF7; - msr = rdmsr(BU_CFG2_MSR); - msr.hi &= uiMask; // set bit 35 to 0 - wrmsr(BU_CFG2_MSR, msr); + msr = rdmsr(BU_CFG2_MSR); + msr.hi &= uiMask; // IcDisSpecTlbWr (bit 35) = 0 + wrmsr(BU_CFG2_MSR, msr); #endif } void post_cache_as_ram(void) { void *resume_backup_memory = NULL; + uint32_t family = amd_fam1x_cpu_family(); struct romstage_handoff *handoff; handoff = romstage_handoff_find_or_add(); @@ -112,7 +113,10 @@ void post_cache_as_ram(void) prepare_romstage_ramstack(resume_backup_memory); /* from here don't store more data in CAR */ - vErrata343(); + if (family < 0x6f) { + /* Family 10h or earlier */ + vErrata343(); + } size_t car_size = car_data_size(); void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); -- cgit v1.2.3