From 420faca0d0152a70e9855b78e028efe5bd3e3448 Mon Sep 17 00:00:00 2001 From: Frank Vibrans Date: Mon, 14 Feb 2011 18:42:12 +0000 Subject: Add AMD cpu wrapper code. Patch 4 of 8. This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code. Signed-off-by: Frank Vibrans Acked-by: Stefan Reinauer Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/agesa_wrapper/family14/apic_timer.c | 58 +++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 src/cpu/amd/agesa_wrapper/family14/apic_timer.c (limited to 'src/cpu/amd/agesa_wrapper/family14/apic_timer.c') diff --git a/src/cpu/amd/agesa_wrapper/family14/apic_timer.c b/src/cpu/amd/agesa_wrapper/family14/apic_timer.c new file mode 100644 index 0000000000..26d3f88e49 --- /dev/null +++ b/src/cpu/amd/agesa_wrapper/family14/apic_timer.c @@ -0,0 +1,58 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include +#include +#include +#include + +/* NOTE: We use the APIC TIMER register is to hold flags for AP init during + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). + */ + + +void init_timer(void) +{ + /* Set the apic timer to no interrupts and periodic mode */ + lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); + + /* Set the divider to 1, no divider */ + lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); + + /* Set the initial counter to 0xffffffff */ + lapic_write(LAPIC_TMICT, 0xffffffff); +} + + +void udelay(u32 usecs) +{ + u32 start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ + ticks = usecs * 200; + start = lapic_read(LAPIC_TMCCT); + do { + value = lapic_read(LAPIC_TMCCT); + } while((start - value) < ticks); + +} -- cgit v1.2.3