From fec6fa799ce16eabec0add9bfe6ab5222921f612 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 12 Jul 2017 16:30:47 +0300 Subject: vendorcode/amd/agesa: Tidy up gcccar.inc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change register preservations and fix comments about register usage accordingly. Do this to avoid use of %mm0-2 registers inside macros defined in gcccar.inc, as future implementation of C_BOOTBLOCK_ENVIRONMENT will use them as well. Adjust caller side accordingly. Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b Signed-off-by: Marshall Dawson Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20579 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/cpu/amd/agesa/cache_as_ram.inc | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'src/cpu/amd/agesa') diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 8038177c7c..cfad2f7d1a 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -32,7 +32,7 @@ cache_as_ram_setup: /* Preserve BIST. */ - movl %eax, %ebp + movd %eax, %mm0 post_code(0xa0) @@ -45,7 +45,6 @@ cache_as_ram_setup: post_code(0xa1) - /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK /* Align the stack. */ @@ -96,19 +95,18 @@ cache_as_ram_setup: #endif - /* Calling conventions preserve BIST in %ebp. */ - call early_all_cores /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 pushl $0x0 - pushl %ebp + movd %mm0, %eax /* bist */ + pushl %eax call romstage_main - movl %eax, %ebx + movl %eax, %esp -/* Register %ebx is new stacktop for remaining of romstage. +/* Register %esp is new stacktop for remaining of romstage. * It is the only register preserved in AMD_DISABLE_STACK. */ @@ -125,7 +123,6 @@ disable_cache_as_ram: andl $0x9fffffff, %eax movl %eax, %cr0 - movl %ebx, %esp call romstage_after_car /* Should never see this postcode */ -- cgit v1.2.3