From 9a458e4e58edbfc154dce007961514b5c31cf7aa Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 1 Nov 2022 23:30:21 +0100 Subject: {cpu/nb}/amd/family15tn: Remove platform This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69116 Reviewed-by: Elyes Haouas Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/amd/agesa/Kconfig | 2 - src/cpu/amd/agesa/Makefile.inc | 1 - src/cpu/amd/agesa/family15tn/Kconfig | 7 -- src/cpu/amd/agesa/family15tn/Makefile.inc | 12 --- src/cpu/amd/agesa/family15tn/acpi/cpu.asl | 48 ----------- src/cpu/amd/agesa/family15tn/chip_name.c | 7 -- src/cpu/amd/agesa/family15tn/fixme.c | 51 ------------ src/cpu/amd/agesa/family15tn/model_15_init.c | 114 --------------------------- src/cpu/amd/agesa/family15tn/udelay.c | 45 ----------- 9 files changed, 287 deletions(-) delete mode 100644 src/cpu/amd/agesa/family15tn/Kconfig delete mode 100644 src/cpu/amd/agesa/family15tn/Makefile.inc delete mode 100644 src/cpu/amd/agesa/family15tn/acpi/cpu.asl delete mode 100644 src/cpu/amd/agesa/family15tn/chip_name.c delete mode 100644 src/cpu/amd/agesa/family15tn/fixme.c delete mode 100644 src/cpu/amd/agesa/family15tn/model_15_init.c delete mode 100644 src/cpu/amd/agesa/family15tn/udelay.c (limited to 'src/cpu/amd/agesa') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b224fc35a1..f6c4f16199 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -2,7 +2,6 @@ config CPU_AMD_AGESA bool - default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n select ARCH_X86 @@ -46,5 +45,4 @@ config ENABLE_MRC_CACHE endif # CPU_AMD_AGESA -source "src/cpu/amd/agesa/family15tn/Kconfig" source "src/cpu/amd/agesa/family16kb/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 31c2635de3..5d8f6dfd87 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig deleted file mode 100644 index 0cccaa6f00..0000000000 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config CPU_AMD_AGESA_FAMILY15_TN - bool - select IDS_OPTIONS_HOOKED_UP - select SMM_ASEG - select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc deleted file mode 100644 index ca51196c66..0000000000 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += fixme.c - -ramstage-y += fixme.c -ramstage-y += chip_name.c -ramstage-y += model_15_init.c - -smm-y += udelay.c - -subdirs-y += ../../mtrr -subdirs-$(CONFIG_SMM_LEGACY_ASEG) += ../../smm diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl deleted file mode 100644 index ede5021e03..0000000000 --- a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Processor Object - * - */ -Scope (\_SB) { /* define processor scope */ - - Device (P000) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - - Device (P001) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - - Device (P002) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - - Device (P003) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - - Device (P004) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - - Device (P005) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - - Device (P006) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - - Device (P007) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } -} /* End _SB scope */ diff --git a/src/cpu/amd/agesa/family15tn/chip_name.c b/src/cpu/amd/agesa/family15tn/chip_name.c deleted file mode 100644 index 6c143f5dde..0000000000 --- a/src/cpu/amd/agesa/family15tn/chip_name.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -struct chip_operations cpu_amd_agesa_family15tn_ops = { - CHIP_NAME("AMD CPU Family 15h Model 10h-1Fh") -}; diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c deleted file mode 100644 index 7b8b70df41..0000000000 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -void amd_initcpuio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); -} diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c deleted file mode 100644 index c256ffcabf..0000000000 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void model_15_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); - - msr_t msr; - int msrno; - unsigned int cpu_idx; -#if CONFIG(LOGICAL_CPUS) - u32 siblings; -#endif - - /* - * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set - * by coreboot. - */ - disable_cache(); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - if (acpi_is_wakeup_s3()) - restore_mtrr(); - - x86_mtrr_check(); - enable_cache(); - - /* zero the machine check error status registers */ - mca_clear_status(); - -#if CONFIG(LOGICAL_CPUS) - siblings = get_cpu_count() - 1; // minus BSP - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - if (CONFIG(HAVE_SMI_HANDLER)) { - cpu_idx = cpu_info()->index; - printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); - - /* Set SMM base address for this CPU */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (cpu_idx * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* Enable the SMM memory window */ - msr = rdmsr(SMM_MASK_MSR); - msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(SMM_MASK_MSR, msr); - } - - /* Write protect SMM space with SMMLOCK. */ - lock_smm(); -} - -static struct device_operations cpu_dev_ops = { - .init = model_15_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ - { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */ - { 0, 0 }, -}; - -static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c deleted file mode 100644 index 9bd4f9f879..0000000000 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * udelay() implementation for SMI handlers - * This is neat in that it never writes to hardware registers, and thus does - * not modify the state of the hardware while servicing SMIs. - */ - -#include -#include -#include -#include -#include - -void udelay(uint32_t us) -{ - uint8_t fid, did, pstate_idx; - uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; - msr_t msr; - const uint64_t tsc_base = 100000000; - - /* Get initial timestamp before we do the math */ - tsc_start = rdtscll(); - - /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(PS_STS_REG); - pstate_idx = msr.lo & 0x07; - - /* Get FID and VID for current P-State */ - msr = rdmsr(PSTATE_0_MSR + pstate_idx); - - /* Extract the FID and VID values */ - fid = msr.lo & 0x3f; - did = (msr.lo >> 6) & 0x7; - - /* Calculate the CPU clock (from base freq of 100MHz) */ - tsc_clock = tsc_base * (fid + 0x10) / (1 << did); - - /* Now go on and wait */ - tsc_wait_ticks = (tsc_clock / 1000000) * us; - - do { - tsc_now = rdtscll(); - } while (tsc_now - tsc_wait_ticks < tsc_start); -} -- cgit v1.2.3