From 1b12b64dab57151d1f04d13d09c1afbf16a7485f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Sun, 24 Nov 2019 16:32:05 +0100
Subject: AGESA, binaryPI: implement C bootblock
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Modify CAR setup to work in bootblock. Provide bootblock C file with
necessary C bootblock functions. Additionally chache the ROM and set
the MMCONF base before jumping to bootblock main.

Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/amd/agesa/Kconfig | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/cpu/amd/agesa')

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 5e1ff1d6c9..2c8f9c5e37 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -49,6 +49,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x4000
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x8000
+
 config ENABLE_MRC_CACHE
 	bool "Use cached memory configuration"
 	default n
-- 
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