From f8e9449df084d0ccd1a98e756b37343e509c6b67 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 3 Sep 2017 13:44:03 +0300 Subject: AGESA: Drop old ACPI S3 resume path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixed ACPI S3 support will use POSTCAR_STAGE and no longer uses the code removed here. Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21380 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/amd/agesa/s3_resume.c | 53 ------------------------------------------- 1 file changed, 53 deletions(-) delete mode 100644 src/cpu/amd/agesa/s3_resume.c (limited to 'src/cpu/amd/agesa/s3_resume.c') diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c deleted file mode 100644 index 34717b9618..0000000000 --- a/src/cpu/amd/agesa/s3_resume.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "s3_resume.h" -#include - -void set_resume_cache(void) -{ - msr_t msr; - - /* disable fixed mtrr for now, it will be enabled by mtrr restore */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); - wrmsr(SYSCFG_MSR, msr); - - /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ - msr.lo = 0 | MTRR_TYPE_WRBACK; - msr.hi = 0; - wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; - msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(0), msr); - - /* Set the default memory type and disable fixed and enable variable MTRRs */ - msr.hi = 0; - msr.lo = (1 << 11); - wrmsr(MTRR_DEF_TYPE_MSR, msr); - - enable_cache(); -} -- cgit v1.2.3