From 300caced970febaa84357e60cee872553a872af5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 16 Dec 2014 19:50:47 +0200 Subject: AGESA: Refactor OEM S3 storage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use function prototypes that match more closely with the structure of other OEM hooks in agesawrappers. Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/cpu/amd/agesa/s3_resume.c | 57 +++++++------------------------------------ 1 file changed, 9 insertions(+), 48 deletions(-) (limited to 'src/cpu/amd/agesa/s3_resume.c') diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 2ba684650a..9789cc402e 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -34,18 +34,16 @@ #include #include "s3_resume.h" +#ifndef __PRE_RAM__ void restore_mtrr(void) { + volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); u32 msr; - volatile UINT32 *msrPtr; msr_t msr_data; - printk(BIOS_SPEW, "%s\n", __func__); - - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - msrPtr = (UINT32 *)(pos + sizeof(UINT32)); + if (!msrPtr) + return; disable_cache(); @@ -103,6 +101,8 @@ void restore_mtrr(void) wrmsr(SYS_CFG, msr_data); } +#endif + #ifdef __PRE_RAM__ static void *backup_resume(void) { @@ -138,10 +138,6 @@ static void move_stack_high_mem(void) #endif #ifndef __PRE_RAM__ -/* FIXME: Why store MTRR in SPI, just use CBMEM ? */ -#define S3_DATA_MTRR_SIZE 0x1000 -static u8 mtrr_store[S3_DATA_MTRR_SIZE]; - static void write_mtrr(u8 **p_nvram_pos, unsigned idx) { msr_t msr_data; @@ -151,13 +147,12 @@ static void write_mtrr(u8 **p_nvram_pos, unsigned idx) *p_nvram_pos += sizeof(msr_data); } -void OemAgesaSaveMtrr(void) +void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) { + u8 *nvram_pos = mtrr_store; msr_t msr_data; u32 i; - u8 *nvram_pos = (u8 *) mtrr_store; - /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -187,44 +182,10 @@ void OemAgesaSaveMtrr(void) /* TOM2 */ write_mtrr(&nvram_pos, 0xC001001D); -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store); -#endif -} - -u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) -{ -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - spi_SaveS3info(pos, size, Data, DataSize); -#endif - return AGESA_SUCCESS; + *mtrr_store_size = nvram_pos - (u8*) mtrr_store; } #endif -void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) -{ - AMD_CONFIG_PARAMS StdHeader; - - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - - if (S3DataType == S3DataTypeNonVolatile) { - *DataSize = *(UINT32 *) pos; - *Data = (void *) (pos + sizeof(UINT32)); - } else if (S3DataType == S3DataTypeVolatile) { - u32 len = *(UINT32 *) pos; - void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); - *DataSize = len; - *Data = dst; - } -} - #ifdef __PRE_RAM__ static void set_resume_cache(void) { -- cgit v1.2.3