From 105da50df4fe6073575a2eb6247d916746b6143e Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Sat, 5 Jan 2013 12:17:46 +0800 Subject: AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/cpu/amd/agesa/family15tn/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/amd/agesa/family15tn') diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 8f3a9ffb44..7459818b77 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY15_TN config CPU_ADDR_BITS int - default 36 + default 48 depends on CPU_AMD_AGESA_FAMILY15_TN config CPU_SOCKET_TYPE -- cgit v1.2.3