From 520717dff196e1d1ed61f72a8abadbc114ee6ba1 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 15 Dec 2019 21:37:48 +0200 Subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/fixme.c | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'src/cpu/amd/agesa/family14') diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c9d30396aa..be7c635471 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -61,25 +61,6 @@ void amd_initcpuio(void) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} - void amd_initenv(void) { AMD_INTERFACE_PARAMS AmdParamStruct; -- cgit v1.2.3