From f6fe2f1286f2551ae8d9732f949a51eb6c975363 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 21 Nov 2016 11:26:48 +0200 Subject: AGESA binaryPI: Fix cache-as-ram for x86_64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AMD_ENABLE_STACK was not called on x86_64 path for AGESA, while it was for binaryPI. Comments on BIST and cpu_init_detected were reversed, so fix those too. Change-Id: I0ddfaf51feb386a56d488c29d60171b05ff6fbc4 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17551 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Edward O'Callaghan --- src/cpu/amd/agesa/cache_as_ram.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/cpu/amd/agesa/cache_as_ram.inc') diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 293e9a5077..24db6001ea 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -61,6 +61,8 @@ cache_as_ram_setup: post_code(0xa1) + AMD_ENABLE_STACK + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -103,10 +105,10 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the BIST result */ + /* Pass the cpu_init_detected */ cvtsd2si %xmm1, %esi - /* Pass the cpu_init_detected */ + /* Pass the BIST result */ cvtsd2si %xmm0, %edi /* align the stack */ @@ -117,7 +119,6 @@ cache_as_ram_setup: .code32 #else - AMD_ENABLE_STACK /* Restore the BIST result */ cvtsd2si %xmm0, %edx -- cgit v1.2.3