From 77d3c4b69003a9b5d864190be334f7239623789c Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 22 Nov 2016 12:00:52 +0200 Subject: AGESA: Fork for new cache-as-ram init code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To gradually consolidate and improve AGESA board romstages, fork the original CAR setup code as a separate file. It becomes too messy with preprocessor to attempt make changes within the same file, and at end of patchset original becomes obsolete. Change-Id: I256b675b1ab9e13c2bcc956e0d67c6c03e91f2ed Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Martin Roth --- src/cpu/amd/agesa/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/amd/agesa/Makefile.inc') diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 60bae120bc..9853d63c5f 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -23,7 +23,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c ramstage-y += s3_mtrr.c +ifeq ($(CONFIG_AGESA_LEGACY), y) +cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc +else cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +endif romstage-y += heapmanager.c ramstage-y += heapmanager.c -- cgit v1.2.3