From e33c50d74c518e0ebe1f2d8e88cebd023bb94bcf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 6 Oct 2019 17:39:44 +0200 Subject: cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZE AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Paul Menzel --- src/cpu/amd/agesa/Kconfig | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'src/cpu/amd/agesa/Kconfig') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index f21bf5467f..b1fde2dcf7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -28,20 +28,10 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG + select NO_FIXED_XIP_ROM_SIZE if CPU_AMD_AGESA -config XIP_ROM_SIZE - hex - default 0x100000 - help - Overwride the default write through caching size as 1M Bytes. - On some AMD platforms, one socket supports 2 or more kinds of - processor family, compiling several CPU families agesa code - will increase the romstage size. - In order to execute romstage in place on the flash ROM, - more space is required to be set as write through caching. - config UDELAY_LAPIC_FIXED_FSB int default 200 -- cgit v1.2.3