From 24ab1c5db6a48f27d1541f8f356127a14111358e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 25 Nov 2019 11:57:28 +0530 Subject: soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/cpu/Makefile.inc | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/cpu/Makefile.inc') diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index b80c30d72b..4b5d67b908 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -59,9 +59,4 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode - -ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) -cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) -else cpu_microcode_blob.bin-align := 16 -endif -- cgit v1.2.3