From ca374d455cad29c546a2d310c331a4ae431c33f9 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 18 Jan 2008 16:16:45 +0000 Subject: rename linuxbios_* files, too. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/config/Config.lb | 10 ++-- src/config/coreboot_apc.ld | 100 ++++++++++++++++++++++++++++++++++++ src/config/coreboot_ram.ld | 121 ++++++++++++++++++++++++++++++++++++++++++++ src/config/linuxbios_apc.ld | 100 ------------------------------------ src/config/linuxbios_ram.ld | 121 -------------------------------------------- 5 files changed, 226 insertions(+), 226 deletions(-) create mode 100644 src/config/coreboot_apc.ld create mode 100644 src/config/coreboot_ram.ld delete mode 100644 src/config/linuxbios_apc.ld delete mode 100644 src/config/linuxbios_ram.ld (limited to 'src/config') diff --git a/src/config/Config.lb b/src/config/Config.lb index 76b44b7c65..e2daee3b45 100644 --- a/src/config/Config.lb +++ b/src/config/Config.lb @@ -44,8 +44,8 @@ makerule coreboot_ram.o end makerule coreboot_ram - depends "coreboot_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions" - action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld coreboot_ram.o" + depends "coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" + action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o" action "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map" end @@ -87,8 +87,8 @@ if CONFIG_AP_CODE_IN_CAR end makerule coreboot_apc - depends "coreboot_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions" - action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld coreboot_apc.o" + depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions" + action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o" action "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map" end @@ -174,7 +174,7 @@ makerule ./romcc end makerule build_opt_tbl - depends "$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/linuxbios_tables.h Makefile.settings Makefile" + depends "$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile" action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" end diff --git a/src/config/coreboot_apc.ld b/src/config/coreboot_apc.ld new file mode 100644 index 0000000000..9bca028ca1 --- /dev/null +++ b/src/config/coreboot_apc.ld @@ -0,0 +1,100 @@ +/* + * Memory map: + * + * DCACHE_RAM_BASE + * : data segment + * : bss segment + * : heap + * : stack + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + * 2006.05 yhlu tailed it to use it for AP code in cache + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = DCACHE_RAM_BASE; + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text : { + _text = .; + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + .rodata : { + _rodata = .; + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + _erodata = .; + } + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + . = ALIGN(0x1000); + _stack = .; + .stack . : { + . = 0x4000; + } + _estack = .; + _heap = .; + .heap . : { + . = ALIGN(4); + } + _eheap = .; + /* The ram segment + * This is all address of the memory resident copy of coreboot. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/config/coreboot_ram.ld b/src/config/coreboot_ram.ld new file mode 100644 index 0000000000..5af6e74100 --- /dev/null +++ b/src/config/coreboot_ram.ld @@ -0,0 +1,121 @@ +/* + * Memory map: + * + * _RAMBASE + * : data segment + * : bss segment + * : heap + * : stack + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = _RAMBASE; + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text : { + _text = .; + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + .rodata : { + _rodata = .; + . = ALIGN(4); + console_drivers = .; + *(.rodata.console_drivers) + econsole_drivers = . ; + . = ALIGN(4); + pci_drivers = . ; + *(.rodata.pci_driver) + epci_drivers = . ; + cpu_drivers = . ; + *(.rodata.cpu_driver) + ecpu_drivers = . ; + *(.rodata) + *(.rodata.*) + /* + * kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + * This breaks the coreboot.strip target. + */ + . = ALIGN(4); + + _erodata = .; + } + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + . = ALIGN(STACK_SIZE); + _stack = .; + .stack . : { + /* Reserve a stack for each possible cpu */ + /* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/ + . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? STACK_SIZE : (CONFIG_MAX_CPUS*STACK_SIZE); + } + _estack = .; + _heap = .; + .heap . : { + /* Reserve 256K for the heap */ + . = HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; + /* The ram segment + * This is all address of the memory resident copy of coreboot. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + _bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); + + _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/config/linuxbios_apc.ld b/src/config/linuxbios_apc.ld deleted file mode 100644 index 9bca028ca1..0000000000 --- a/src/config/linuxbios_apc.ld +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Memory map: - * - * DCACHE_RAM_BASE - * : data segment - * : bss segment - * : heap - * : stack - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - * 2006.05 yhlu tailed it to use it for AP code in cache - */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ -INCLUDE ldoptions - -ENTRY(_start) - -SECTIONS -{ - . = DCACHE_RAM_BASE; - /* - * First we place the code and read only data (typically const declared). - * This get placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } - .rodata : { - _rodata = .; - . = ALIGN(4); - *(.rodata) - *(.rodata.*) - . = ALIGN(4); - _erodata = .; - } - /* - * After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - /* - * bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - . = ALIGN(0x1000); - _stack = .; - .stack . : { - . = 0x4000; - } - _estack = .; - _heap = .; - .heap . : { - . = ALIGN(4); - } - _eheap = .; - /* The ram segment - * This is all address of the memory resident copy of coreboot. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/config/linuxbios_ram.ld b/src/config/linuxbios_ram.ld deleted file mode 100644 index 5af6e74100..0000000000 --- a/src/config/linuxbios_ram.ld +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Memory map: - * - * _RAMBASE - * : data segment - * : bss segment - * : heap - * : stack - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ -INCLUDE ldoptions - -ENTRY(_start) - -SECTIONS -{ - . = _RAMBASE; - /* - * First we place the code and read only data (typically const declared). - * This get placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } - .rodata : { - _rodata = .; - . = ALIGN(4); - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); - pci_drivers = . ; - *(.rodata.pci_driver) - epci_drivers = . ; - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - *(.rodata) - *(.rodata.*) - /* - * kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - * This breaks the coreboot.strip target. - */ - . = ALIGN(4); - - _erodata = .; - } - /* - * After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - /* - * bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - . = ALIGN(STACK_SIZE); - _stack = .; - .stack . : { - /* Reserve a stack for each possible cpu */ - /* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/ - . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? STACK_SIZE : (CONFIG_MAX_CPUS*STACK_SIZE); - } - _estack = .; - _heap = .; - .heap . : { - /* Reserve 256K for the heap */ - . = HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; - /* The ram segment - * This is all address of the memory resident copy of coreboot. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - _bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); - - _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M"); - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} -- cgit v1.2.3