From bb50190bec998b4ec1a6cf4e02f1ae4022b36084 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 17 Mar 2024 11:12:12 +0100 Subject: soc/intel/xeon_sp: Drop RMRR entry for USB Drop RMRR entry for XHCI controller since it's not under BIOS control. There's no USB-PS/2 emulation done in SMM, hence it's not needed. TEST=intel/archercity CRB Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: Shuo Liu --- src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/commonlib/bsd/include') diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 615b8c63f3..b88a0831b9 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -61,7 +61,7 @@ #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 #define CBMEM_ID_STAGEx_RAW 0x57a9e200 -#define CBMEM_ID_STORAGE_DATA 0x53746f72 +#define CBMEM_ID_STORAGE_DATA 0x53746f72 /* deprecated */ #define CBMEM_ID_TPM_CB_LOG 0x54435041 /* TPM log in coreboot-specific format */ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 /* TPM log per TPM 1.2 specification */ #define CBMEM_ID_TIMESTAMP 0x54494d45 -- cgit v1.2.3