From fc934b2da280d64bf42d2947346558f7475d5481 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Wed, 5 Nov 2014 17:51:19 -0800 Subject: mips: add c0 register access plumbing C0 is a coprocessor register set defined in certain MIPS architectures. This patch adds macros necessary to access the registers and a couple of helper macros to access two particular registers needed in the next patch. The definitions come straight from arch/mips/include/asm/mipsregs.h in the 3.14 kernel tree. BRANCH=none BUG=chrome-os-partner:31438 TEST=the following patch demonstrates timer counter C0 register configuration and use. Change-Id: Ia5d52ffa75f2dd66d4cee3a4ed0af5122ccb2113 Signed-off-by: Patrick Georgi Original-Commit-Id: eb3d69eaf1561ca0b995720c24dafe2e6e22707d Original-Change-Id: Ia4b1da40ecc1a03cf1cba0c648d42cd189fbcf93 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/227887 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/mips/include/arch/cpu.h | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'src/arch') diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 0ac9f31700..4f4c376eee 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -40,4 +40,52 @@ struct cpu_info { #endif /* !__PRE_RAM__ */ +/*************************************************************************** + * The following section was copied from arch/mips/include/asm/mipsregs.h in + * the 3.14 kernel tree. + */ + +/* + * Macros to access the system control coprocessor + */ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +/* Shortcuts to access various internal registers, keep adding as needed. */ +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) + +#define C0_CAUSE_DC (1 << 27) +/**************************************************************************/ + #endif /* __MIPS_ARCH_CPU_H */ -- cgit v1.2.3