From ef63c32b5843c8b585804aa7ba37a3e7da2b7b1a Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Mon, 4 Nov 2019 16:21:25 +0100
Subject: arch/riscv: Don't link `stages.c` into ramstage

It's superseded by `ramstage.S`.

Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/riscv/Makefile.inc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/arch')

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0039fab180..16f160e8db 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -140,7 +140,6 @@ ramstage-y += fp_asm.S
 ramstage-y += misaligned.c
 ramstage-y += sbi.c
 ramstage-y += virtual_memory.c
-ramstage-y += stages.c
 ramstage-y += misc.c
 ramstage-y += smp.c
 ramstage-y += boot.c
-- 
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