From ded91fffb833823ea7d71654c1e10696eba0d419 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 11 Sep 2018 10:03:08 +0200 Subject: arch/riscv: Configure delegation only if S-mode is supported MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the FU540 the bootblock runs on a core without lesser privilege modes, so the medeleg/mideleg CSRs are not implemented on that core, leading to a CPU exception when these CSRs are accessed. Configure medeleg/mideleg only if the misa register indicates that S-mode is implemented on the executing RISC-V core. Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/25791 Reviewed-by: Xiang Wang Reviewed-by: Philipp Hug Reviewed-by: Johanna Schander Reviewed-by: Ronald G. Minnich Tested-by: build bot (Jenkins) --- src/arch/riscv/virtual_memory.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src/arch') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 3bee86865d..5b35e811d9 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -52,11 +53,12 @@ void mstatus_init(void) // all other supervisor interrupts. set_csr(mie, MIP_MTIP | MIP_STIP | MIP_SSIP); - // Delegate supervisor timer and other interrupts - // to supervisor mode. - set_csr(mideleg, MIP_STIP | MIP_SSIP); - - set_csr(medeleg, delegate); + // Delegate supervisor timer and other interrupts to supervisor mode, + // if supervisor mode is supported. + if (supports_extension('S')) { + set_csr(mideleg, MIP_STIP | MIP_SSIP); + set_csr(medeleg, delegate); + } // Enable all user/supervisor-mode counters using // v1.10 register addresses. -- cgit v1.2.3