From a9ee61e2538c206c3518f4ede1da6405ad7b1476 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 18 Mar 2015 11:27:25 -0700 Subject: cache: Add arch_program_segment_loaded call to arm and arm64 arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. Use this function in rmodules as well instead of cache_sync_instructions which guarantees sync upto PoC. BUG=chrome-os-partner:37546 BRANCH=None TEST=Boots into depthcharge on foster Change-Id: I64c2dd5e40ea59fa31f300174ca0d0aebcf8041d Signed-off-by: Patrick Georgi Original-Commit-Id: 35ba0b882b86ff2c29ac766e1d65f403c8346247 Original-Change-Id: I964aa09f0cafdaab170606cd4b8f2e027698aee7 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/260908 Original-Reviewed-by: Furquan Shaikh Original-Tested-by: Furquan Shaikh Original-Commit-Queue: Furquan Shaikh Original-Trybot-Ready: Furquan Shaikh Reviewed-on: http://review.coreboot.org/10173 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/arm/armv7/cache.c | 10 ++++++++++ src/arch/arm64/armv8/cache.c | 12 ++++++++++++ 2 files changed, 22 insertions(+) (limited to 'src/arch') diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index 1f762b8f9b..eea514bd4b 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -34,6 +34,7 @@ #include #include +#include void tlb_invalidate_all(void) { @@ -155,3 +156,12 @@ void cache_sync_instructions(void) dsb(); isb(); } + +/* + * For each segment of a program loaded this function is called + * to invalidate caches for the addresses of the loaded segment + */ +void arch_segment_loaded(uintptr_t start, size_t size, int flags) +{ + cache_sync_instructions(); +} diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index db9b3882bc..95f2890ff0 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -36,6 +36,7 @@ #include #include #include +#include void tlb_invalidate_all(void) { @@ -147,3 +148,14 @@ void cache_sync_instructions(void) flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */ icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ } + + +/* + * For each segment of a program loaded this function is called + * to invalidate caches for the addresses of the loaded segment + */ +void arch_segment_loaded(uintptr_t start, size_t size, int flags) +{ + dcache_clean_invalidate_by_mva((void *)start, size); + icache_invalidate_all(); +} -- cgit v1.2.3