From a6a2f9372c492c2e6ca4404b372054b1fd82e1ee Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Nov 2019 19:58:36 +0100 Subject: arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram INVD is called below so if postcar is running in a cached environment it needs to happen. NOTE: postcar cannot execute in a cached environment if clflush is not supported! Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/arch/x86/exit_car.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 806dc9c069..dc356b2cf9 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -2,6 +2,7 @@ #include #include +#include .section ".module_parameters", "aw", @progbits /* stack_top indicates the stack to pull MTRR information from. */ @@ -54,7 +55,14 @@ _start: movl 4(%esp), %eax movl %eax, _cbmem_top_ptr #endif - + /* Make sure _cbmem_top_ptr hits dram before invd */ + movl $1, %eax + cpuid + btl $CPUID_FEATURE_CLFLUSH_BIT, %edx + jz skip_clflush + clflush _cbmem_top_ptr + +skip_clflush: /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car -- cgit v1.2.3