From 9d0cce2087139a2eab447aea3fdebfe44e97c280 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 21 Jun 2016 19:37:03 +0200 Subject: riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/15287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/bootblock.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 07d68ab851..5092ec0405 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -38,10 +38,10 @@ _start: sd t0, 0(t1) la t0, exception_handler - csrw stvec, t0 + csrw mtvec, t0 # clear any pending interrupts - csrwi sip, 0 + csrwi mip, 0 # set up the mstatus register for VM call mstatus_init -- cgit v1.2.3