From 710566093a504f0fecb641661c5379cad268189b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 10 Jun 2016 19:35:16 +0200 Subject: riscv-spike: Move coreboot to 0x80000000 (2GiB) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/riscv/bootblock.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/arch') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 029e9e48a3..e75e1ca407 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -34,8 +34,11 @@ machine_handler: .globl _start _start: +#define STACK_START 0x80800000 /* 2GiB + 8MiB */ +#define STACK_SIZE 0x0000fff0 + // pending figuring out this f-ing toolchain. Hardcode what we know works. - li sp, 0x80FFF0 // stack start + stack size + li sp, STACK_START + STACK_SIZE # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE @@ -43,7 +46,7 @@ _start: call hls_init //poison the stack - li t1, 0x800000 + li t1, STACK_START li t0, 0xdeadbeef sd t0, 0(t1) -- cgit v1.2.3