From 6d0fe9cad003d752af3214ae9a91d7411d582950 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Sun, 7 Apr 2013 17:26:34 -0700 Subject: armv7: specify condition code for msr instruction This adds condition codes when using the msr instruction. Although described as "optional" in the Cortex-A series programmer's guide, our experience with using the msr instruction in the payload suggests that the condition code is not optional and that this only worked in coreboot (and u-boot) because the processor comes up in SVC32 mode. (credit to Gabe Black for finding this, I'm only uploading the patch) Signed-off-by: Gabe Black Signed-off-by: David Hendricks Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b Reviewed-on: http://review.coreboot.org/3037 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/armv7/bootblock.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch') diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c647834c5f..faf5475819 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -58,7 +58,7 @@ reset: mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0xd3 - msr cpsr,r0 + msr cpsr_cxsf,r0 /* * From Cortex-A Series Programmer's Guide: -- cgit v1.2.3