From 58779358362ef0c9ed433c310416a93c8b9c9211 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 29 Mar 2013 13:40:09 -0700 Subject: armv7: remove loop from dcache_mmu_disable() dcache_mmu_disable() no longer needs to have its own iterative loop to select each cache level of cache since dcache_clean_invalidate_all() does that now. Change-Id: I5ca273f98943981b943c1c1622f4574d7133fb50 Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/2967 Reviewed-by: Gabe Black Tested-by: build bot (Jenkins) --- src/arch/armv7/lib/cache.c | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) (limited to 'src/arch') diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index c7283f14cf..04eaa88c7c 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -237,37 +237,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) void dcache_mmu_disable(void) { - uint32_t sctlr, clidr; - int level; - - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x0: - /* no cache */ - break; - case 0x2: - case 0x4: - /* dcache only or unified cache */ - csselr = level << 1; - write_csselr(csselr); - dcache_clean_invalidate_all(); - break; - case 0x3: - /* separate icache and dcache */ - csselr = level << 1; - write_csselr(csselr); - dcache_clean_invalidate_all(); - break; - default: - /* reserved */ - break; - } - } + uint32_t sctlr; + dcache_clean_invalidate_all(); sctlr = read_sctlr(); sctlr &= ~(SCTLR_C | SCTLR_M); write_sctlr(sctlr); -- cgit v1.2.3