From 531704ed71c48a41fba23948fe8f9104c5e1f470 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 10 Feb 2010 11:56:21 +0000 Subject: Drop src/config alltogether - drop two "newconfig" based files - drop two obsolete doxygen config files and check in our latest Doxyfile.coreboot (that has been used to build coreboot online documentation since 2005 or so) - move two i386 specific linker scripts to src/arch/i386 Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/i386/Makefile.inc | 4 +- src/arch/i386/coreboot_apc.ld | 100 ++++++++++++++++++++++++++++++++ src/arch/i386/coreboot_ram.ld | 132 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+), 2 deletions(-) create mode 100644 src/arch/i386/coreboot_apc.ld create mode 100644 src/arch/i386/coreboot_ram.ld (limited to 'src/arch') diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc index d6b68e2524..db5171920c 100644 --- a/src/arch/i386/Makefile.inc +++ b/src/arch/i386/Makefile.inc @@ -45,9 +45,9 @@ $(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc8 ####################################################################### # Build the coreboot_ram (stage 2) -$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions +$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/i386/coreboot_ram.ld #ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/coreboot_ram.ld $(obj)/coreboot_ram.o $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map $(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) diff --git a/src/arch/i386/coreboot_apc.ld b/src/arch/i386/coreboot_apc.ld new file mode 100644 index 0000000000..d7820aafe1 --- /dev/null +++ b/src/arch/i386/coreboot_apc.ld @@ -0,0 +1,100 @@ +/* + * Memory map: + * + * CONFIG_DCACHE_RAM_BASE + * : data segment + * : bss segment + * : heap + * : stack + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + * 2006.05 yhlu tailed it to use it for AP code in cache + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = CONFIG_DCACHE_RAM_BASE; + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text : { + _text = .; + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + .rodata : { + _rodata = .; + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + _erodata = .; + } + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + . = ALIGN(0x1000); + _stack = .; + .stack . : { + . = 0x4000; + } + _estack = .; + _heap = .; + .heap . : { + . = ALIGN(4); + } + _eheap = .; + /* The ram segment + * This is all address of the memory resident copy of coreboot. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + _bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld new file mode 100644 index 0000000000..afdf8a5522 --- /dev/null +++ b/src/arch/i386/coreboot_ram.ld @@ -0,0 +1,132 @@ +/* + * Memory map: + * + * CONFIG_RAMBASE + * : data segment + * : bss segment + * : heap + * : stack + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = CONFIG_RAMBASE; + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text : { + _text = .; + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + .rodata : { + _rodata = .; + . = ALIGN(4); + console_drivers = .; + *(.rodata.console_drivers) + econsole_drivers = . ; + . = ALIGN(4); + pci_drivers = . ; + *(.rodata.pci_driver) + epci_drivers = . ; + cpu_drivers = . ; + *(.rodata.cpu_driver) + ecpu_drivers = . ; + *(.rodata) + *(.rodata.*) + /* + * kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + * This breaks the coreboot.rom target. + */ + . = ALIGN(4); + + _erodata = .; + } + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + + .sdata : { + _SDA_BASE_ = .; + *(.sdata) + } + + .sdata2 : { + _SDA2_BASE_ = .; + *(.sdata2) + } + + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + . = ALIGN(CONFIG_STACK_SIZE); + _stack = .; + .stack . : { + /* Reserve a stack for each possible cpu */ + /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/ + . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); + } + _estack = .; + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; + /* The ram segment + * This is all address of the memory resident copy of coreboot. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP"); + + _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} -- cgit v1.2.3