From 4796c32ad60933bd8c23729684414121097b0445 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 15 Mar 2017 08:07:22 +0200 Subject: ramstage: Align stack to 16 bytes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some SSE instructions could take 128bit memory operands from stack. AGESA vendorcode was always built with SSE enabled, but until now stack alignment was not known to cause major issues. Seems like GCC-6.3 more likely emits instructions that depend on the 16 byte alignment of stack. Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/arch/x86/c_start.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch') diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 29d3a538b4..9ad2698483 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -110,6 +110,8 @@ _start: */ post_code(POST_PRE_HARDWAREMAIN) /* post fe */ + andl $0xFFFFFFF0, %esp + #if CONFIG_GDB_WAIT call gdb_hw_init call gdb_stub_breakpoint -- cgit v1.2.3