From 3965a522c23ea50b1a861b89a8215a524caa35f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 22 Aug 2016 19:37:15 +0200 Subject: arch/riscv: Enable U-mode/S-mode counters (stime, etc.) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/16262 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/virtual_memory.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/arch') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 98b7edca4e..fab7d90d70 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -218,4 +218,8 @@ void mstatus_init(void) | (1 << CAUSE_FAULT_STORE) | (1 << CAUSE_USER_ECALL) ); + + /* Enable all user/supervisor-mode counters */ + write_csr(mscounteren, 0b111); + write_csr(mucounteren, 0b111); } -- cgit v1.2.3