From 36e62c2516ef46e726af79da3d14dfa416e468ab Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Tue, 6 Aug 2013 17:32:41 -0700 Subject: armv7: add wrappers to read/write L2ACTLR This adds inline wrappers to read the L2 cache auxiliary control register (L2ACTLR). Signed-off-by: David Hendricks Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f Reviewed-on: https://gerrit.chromium.org/gerrit/64861 Commit-Queue: David Hendricks Reviewed-by: David Hendricks Tested-by: David Hendricks Reviewed-on: http://review.coreboot.org/4437 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/armv7/include/arch/cache.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/arch') diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 5166af3f9b..8a14ff9388 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val) isb(); } +/* read L2 Auxiliary Control Register (L2ACTLR) */ +static inline uint32_t read_l2actlr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + return val; +} + +/* write L2 Auxiliary Control Register (L2ACTLR) */ +static inline void write_l2actlr(uint32_t val) +{ + asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ static inline uint32_t read_sctlr(void) { -- cgit v1.2.3