From 33e5df3f25b4594c008788625cd405d988fc6e6b Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 3 Jul 2013 10:51:34 +0300 Subject: Set PCI bus operations at buildtime for ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/x86/include/arch/pci_ops.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/arch') diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index e6027b7038..fa293173d5 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -22,8 +22,4 @@ static inline const struct pci_bus_operations *pci_config_default(void) #endif } -static inline void pci_set_method(device_t dev) -{ - dev->ops->ops_pci_bus = pci_config_default(); -} #endif /* ARCH_I386_PCI_OPS_H */ -- cgit v1.2.3