From 11093995e4cddfc6db16ad654c3e0d39440f74ff Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Sat, 29 Nov 2014 14:35:49 -0800 Subject: mips: disable caches in bootblock startup code Until proper MIPS cache management is available it is necessary to disable data and instruction caches, otherwise code placed in memory stays in data cache and is not available for instruction fetched. BRANCH=none BUG=chrome-os-partner:31438,chrome-os-partner:34127 TEST=coreboot loading rombase and rambase now succeeds. Change-Id: I4147e1325edc0b9bb951cd7ce18d5f104f3eaec0 Signed-off-by: Stefan Reinauer Original-Commit-Id: 93d5bfa1d01fbbabbabef33a22287ceeea28b15b Original-Change-Id: Ib195ed6e5f08ccaa6bbe3325c2199171bfb63b88 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/232191 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9569 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/mips/bootblock.S | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/arch') diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index 8899fe0a97..ed31b24cfa 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -36,6 +36,16 @@ _start: bne $t0, $t1, 1b addi $t0, $t0, 4 + /* + * Disable caches for now, proper cache management is coming soon. + * http://crosbug.com/p/34127 + */ + mfc0 $t0, $16 + li $t1, -8 + and $t0, $t0, $t1 + ori $t0, $t0, 2 + mtc0 $t0, $16 + /* Run main */ b main -- cgit v1.2.3