From 8c9a89de9961e7029835e987cb0f705b7efa77a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 08:14:57 +0300 Subject: arch/x86/ioapic: Drop irq_on_fsb as a configurable item MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 8 -------- src/arch/x86/include/arch/ioapic.h | 4 ++-- src/arch/x86/ioapic.c | 17 +++++++++-------- 3 files changed, 11 insertions(+), 18 deletions(-) (limited to 'src/arch/x86') diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a488b55d0a..6a25daeed2 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -172,14 +172,6 @@ config CMOS_DEFAULT_FILE default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT -config IOAPIC_INTERRUPTS_ON_FSB - bool - default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - -config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - bool - default n - config HPET_ADDRESS_OVERRIDE def_bool n diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 839dba4977..372cb79e9f 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -34,8 +34,8 @@ u8 get_ioapic_version(void *ioapic_base); void setup_ioapic(void *ioapic_base, u8 ioapic_id); void clear_ioapic(void *ioapic_base); -void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, - bool enable_virtual_wire); +void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire); #endif #endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index dc88de1a8e..d2f65fdaf3 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -119,13 +119,8 @@ u8 get_ioapic_version(void *ioapic_base) return io_apic_read(ioapic_base, 0x01) & 0xff; } -void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, - bool enable_virtual_wire) +void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb) { - int first = 0, last; - - set_ioapic_id(ioapic_base, ioapic_id); - if (irq_on_fsb) { /* * For the Pentium 4 and above APICs deliver their interrupts @@ -139,6 +134,13 @@ void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); } +} + +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire) +{ + int first = 0, last; + + set_ioapic_id(ioapic_base, ioapic_id); if (enable_virtual_wire) { route_i8259_irq0(ioapic_base); @@ -152,6 +154,5 @@ void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, void setup_ioapic(void *ioapic_base, u8 ioapic_id) { - setup_ioapic_helper(ioapic_base, ioapic_id, - CONFIG(IOAPIC_INTERRUPTS_ON_FSB), true); + setup_ioapic_helper(ioapic_base, ioapic_id, true); } -- cgit v1.2.3