From 67d95185865651aecb7ef3d8d343ec3cb9e60f77 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 17 May 2023 17:37:17 +0200 Subject: arch/x86: Don't allow hw floating point operations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even though coreboot does not allow floating point operations some compilers like clang generate code using hw floating point registers, e.g. SSE %XMMx registers on 64bit code by default. Floating point operations need to be enabled in hardware for this to work (CR4). Also in SMM we explicitly need to save and restore floating point registers for this reason. If we instruct the compiler to not generate code with FPU ops, this simplifies our code as we can skip that step. With clang this reduces the binary size a bit. For instance ramstage for qemu/Q35 drops from 216600 bytes decompressed to 212768. TEST: See that with x86_64 bit and clang coreboot reaches the payload without setting the CR4_OSFXSR bit in CR4. Without this change it would bootloop very early in the bootblock on Qemu Q35. Signed-off-by: Arthur Heymans Change-Id: Ib8590c55e7aed1ece2aa23b8ea99463396435e11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75316 Reviewed-by: Julius Werner Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/x86/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/arch/x86') diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4ac30ca270..1c92816547 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -301,6 +301,10 @@ target-objcopy=-O elf64-x86-64 -B i386:x86-64 LD_MACHINE =-m elf_x86_64 endif +# Make sure generated code does not use XMMx and MMx registers +CFLAGS_x86_32 += -mno-mmx -mno-sse +CFLAGS_x86_64 += -mno-mmx -mno-sse + ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_MP_TABLE),y) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/mptable.c),) -- cgit v1.2.3