From 4f14cd8a39e65811af08296633842289efa42927 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Wed, 18 Dec 2019 19:40:48 +0200
Subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
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If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.

This also adds board reset for failing to load postcar
from stage cache.

Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/arch/x86/postcar_loader.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/arch/x86')

diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b53cbf82af..ee2c01b2fc 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -19,6 +19,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <program_loading.h>
+#include <reset.h>
 #include <rmodule.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>
@@ -208,6 +209,12 @@ void postcar_enable_tseg_cache(struct postcar_frame *pcf)
 				MTRR_TYPE_WRBACK);
 }
 
+static void postcar_cache_invalid(void)
+{
+	printk(BIOS_ERR, "postcar cache invalid.\n");
+	board_reset();
+}
+
 void run_postcar_phase(struct postcar_frame *pcf)
 {
 	struct prog prog =
@@ -222,6 +229,9 @@ void run_postcar_phase(struct postcar_frame *pcf)
 		   parameters between S3 resume and normal boot. On the
 		   platforms where the values are the same it's a nop. */
 		finalize_load(prog.arg, pcf->stack);
+
+		if (prog_entry(&prog) == NULL)
+			postcar_cache_invalid();
 	} else
 		load_postcar_cbfs(&prog, pcf);
 
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