From cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 17 Aug 2019 20:51:08 +0300 Subject: soc/intel: Use common romstage code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to . Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/romstage.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/arch/x86/include') diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 42c9fbb6cd..7816a7c0bc 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -18,6 +18,8 @@ #include #include +void mainboard_romstage_entry(void); + /* * Support setting up a stack frame consisting of MTRR information * for use in bootstrapping the caching attributes after cache-as-ram @@ -61,6 +63,20 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf); */ void *postcar_commit_mtrrs(struct postcar_frame *pcf); +/* + * fill_postcar_frame() is called after raminit completes and right before + * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() + * to tag memory ranges as cacheable to speed up execution of postcar and + * early ramstage. + */ +void fill_postcar_frame(struct postcar_frame *pcf); + +/* + * prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void prepare_and_run_postcar(struct postcar_frame *pcf); + /* * Load and run a program that takes control of execution that * tears down CAR and loads ramstage. The postcar_frame object -- cgit v1.2.3