From 8edc6dc91f4a46cca81f99101fb13423615c586a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 22 Aug 2019 11:30:52 +0530 Subject: arch/x86: Cache the TSEG region at the top of ram MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds new API for enabling caching for the TSEG region and setting up required MTRR for next stage. BUG=b:140008206 TEST=Build and boot CML-Hatch. Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki --- src/arch/x86/include/arch/romstage.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/arch/x86/include') diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 2ac225875f..15c93f24bd 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -88,4 +88,13 @@ void run_postcar_phase(struct postcar_frame *pcf); */ void late_car_teardown(void); +/* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ +void postcar_enable_tseg_cache(struct postcar_frame *pcf); + #endif /* __ARCH_ROMSTAGE_H__ */ -- cgit v1.2.3