From 3f9a62e5ade9bf2461c93ac8c6b52c4bdca09742 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 20 Jun 2013 20:25:21 +0300 Subject: Add pci_devfn_t and use with __SIMPLE_DEVICE__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/include/arch/io.h | 22 ++++++++++++++-------- src/arch/x86/include/arch/pci_io_cfg.h | 12 ++++++------ src/arch/x86/include/arch/pci_mmio_cfg.h | 18 +++++++++--------- 3 files changed, 29 insertions(+), 23 deletions(-) (limited to 'src/arch/x86/include') diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 3b61e85b07..859146578b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -210,7 +210,10 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +/* FIXME: Sources for romstage still use device_t. */ +typedef u32 device_t; + +typedef u32 pci_devfn_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore @@ -220,23 +223,26 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha #include #include -static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) +void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value) { pci_write_config8(dev, where, pci_read_config8(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) +void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value) { pci_write_config16(dev, where, pci_read_config16(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) +void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) { pci_write_config32(dev, where, pci_read_config32(dev, where) | value); } #define PCI_DEV_INVALID (0xffffffffU) -static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) +static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -248,7 +254,7 @@ static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device(unsigned pci_id, device_t dev) +static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) { for(; dev <= PCI_DEV(255|(((1< static inline __attribute__((always_inline)) -uint8_t pci_io_read_config8(device_t dev, unsigned where) +uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -34,7 +34,7 @@ uint8_t pci_io_read_config8(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -uint16_t pci_io_read_config16(device_t dev, unsigned where) +uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -47,7 +47,7 @@ uint16_t pci_io_read_config16(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -uint32_t pci_io_read_config32(device_t dev, unsigned where) +uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -60,7 +60,7 @@ uint32_t pci_io_read_config32(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -73,7 +73,7 @@ void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) } static inline __attribute__((always_inline)) -void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +void pci_io_write_config16(pci_devfn_t dev, unsigned where, uint16_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -86,7 +86,7 @@ void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) } static inline __attribute__((always_inline)) -void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 545be236c2..b62a2166b9 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -26,7 +26,7 @@ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) +u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -34,7 +34,7 @@ u8 pcie_read_config8(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) +u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~1); @@ -42,7 +42,7 @@ u16 pcie_read_config16(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) +u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~3); @@ -50,7 +50,7 @@ u32 pcie_read_config32(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) +void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -58,7 +58,7 @@ void pcie_write_config8(device_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) +void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~1); @@ -66,7 +66,7 @@ void pcie_write_config16(device_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) +void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~3); @@ -74,21 +74,21 @@ void pcie_write_config32(device_t dev, unsigned int where, u32 value) } static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) { u8 value = pcie_read_config8(dev, where); pcie_write_config8(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) { u16 value = pcie_read_config16(dev, where); pcie_write_config16(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) { u32 value = pcie_read_config32(dev, where); pcie_write_config32(dev, where, value | ormask); -- cgit v1.2.3