From 1eff77bc59b77735872e675a8df4f059245e4be7 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 7 Sep 2023 10:33:30 -0700
Subject: arch/x86: Reduce max phys address size for Intel TME capable SoCs

On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.

BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
     went from 45 to 41.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/arch/x86/include/arch/cpu.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'src/arch/x86/include')

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 1355096abe..96cf23bb76 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -316,4 +316,15 @@ size_t get_cache_size(const struct cpu_cache_info *info);
  */
 bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
 
+#if CONFIG(CPU_INTEL_COMMON)
+int get_reserved_phys_addr_bits(void);
+#else
+/* Default implementation */
+static inline int get_reserved_phys_addr_bits(void)
+{
+	/* Default implementation */
+	return 0;
+}
+#endif
+
 #endif /* ARCH_CPU_H */
-- 
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