From 7a7c70b26a9744ec7acac807c98e2aaadd7f422d Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 20 Apr 2018 00:56:57 -0600 Subject: arch/x86: prepare for having an idt in other stages Currently the idt setup and handling is only in ramstage. In order to prepare having an exception handler in other stages move the interrupt vector entry code to its own compilation unit. vec0 and int_hand need to be global so c_start.S references will resolve at link time. BUG=b:72728953 Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/25760 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/arch/x86/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/x86/Makefile.inc') diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc529b29cd..b8cf3a6493 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -323,6 +323,7 @@ ramstage-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c +ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memcpy.c -- cgit v1.2.3