From ca928c6768ba143f619a99cca44f9f8153511270 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 4 Apr 2020 01:47:37 +0200 Subject: arch/x86: Implement RESET_VECTOR_IN_RAM Add support for devices with the reset vector pointing into DRAM. This is a specific implementation that assumes a paradigm of AMD Family 17h (a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's state appears to software like other designs, and then the actual physical addressing becomes recognizable. These systems cannot implement cache-as-RAM as in more traditional x86 products. Therefore instead of reusing CAR names and variables, a substitute called "earlyram" is introduced. This change makes adjustments to CAR-aware files accordingly. Enable NO_XIP_EARLY_STAGES. The first stage is already in DRAM, and running subsequent stages as XIP in the boot device would reduce performance. Finally, add a new early_ram.ld linker file. Because all stages run in DRAM, they can be linked with their .data and .bss as normal, i.e. they don't need to rely on storage available only at a fixed location like CAR systems. The primary purpose of the early_ram.ld is to provide consistent locations for PRERAM_CBMEM_CONSOLE, TIMESTAMP regions, etc. across stages until cbmem is brought online. BUG=b:147042464 TEST=Build for trembyle, and boot to ramstage. $ objdump -h cbfs/fallback/bootblock.debug Idx ,Name ,Size ,VMA ,LMA ,File off Algn 0 ,.text ,000074d0 ,08076000 ,08076000 ,00001000 2**12 1 ,.data ,00000038 ,0807d4d0 ,0807d4d0 ,000084d0 2**2 2 ,.bss ,00000048 ,0807d508 ,0807d508 ,00008508 2**2 3 ,.stack ,00000800 ,0807daf0 ,0807daf0 ,00000000 2**0 4 ,.persistent ,00001cfa ,0807e2f0 ,0807e2f0 ,00000000 2**0 5 ,.reset ,00000010 ,0807fff0 ,0807fff0 ,0000aff0 2**0 6 ,.debug_info ,0002659c ,00000000 ,00000000 ,0000b000 2**0 7 ,.debug_abbrev ,000074a2 ,00000000 ,00000000 ,0003159c 2**0 8 ,.debug_aranges,00000dd0 ,00000000 ,00000000 ,00038a40 2**3 9 ,.debug_line ,0000ad65 ,00000000 ,00000000 ,00039810 2**0 10 ,.debug_str ,00009655 ,00000000 ,00000000 ,00044575 2**0 11 ,.debug_loc ,0000b7ce ,00000000 ,00000000 ,0004dbca 2**0 12 ,.debug_ranges ,000029c0 ,00000000 ,00000000 ,00059398 2**3 Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/35035 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/arch/x86/Kconfig') diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 21107aa48b..11733bd05e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -89,9 +89,10 @@ config X86_RESET_VECTOR config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 + select NO_XIP_EARLY_STAGES help - Select this option if the x86 soc implements custom code to handle the - reset vector in RAM instead of the traditional 0xfffffff0 location. + Select this option if the x86 processor's reset vector is in + preinitialized DRAM instead of the traditional 0xfffffff0 location. # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. @@ -206,6 +207,7 @@ config VERSTAGE_ADDR config POSTCAR_STAGE def_bool y depends on ARCH_X86 + depends on !RESET_VECTOR_IN_RAM config VERSTAGE_DEBUG_SPINLOOP bool -- cgit v1.2.3